Program
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Morning
Session
9h00 - 12h |
Afternoon
Session
13h30 - 16h15 |
Late Afternoon
Session
17h15 - 19h45 |
Evening |
SUNDAY |
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Welcome reception |
MONDAY |
Mark Moir
Transactional Memory Algorithms, Language Features, and Implementation |
Free time |
Marko Vukolic
BFT Systems (slides) |
Dinner |
TUESDAY |
Christos Kozyrakis
Hardware Support for Transactional Memory: the Debut (slides) |
Free time |
Doctoral Session |
Dinner |
WEDNESDAY |
Carlo Ghezzi
Dynamically Evolving Self-Adaptive Software (slides) |
Free time |
Doctoral Session
| Dinner |
THURSDAY |
Panagiota Fatourou
Theory results in Transactional Memory (slides) |
Free time |
Doctoral Session |
Dinner |
FRIDAY |
Paolo Costa
Data Centers and the Art of Doing More with Less (slides) |
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Panagiota Fatourou
Title: Theory results in Transactional Memory
Abstract:
This talk presents a collection of theory results in TM. Specifically, we will study several consistency and progress conditions,
impossibility results and lower bounds, as well as design decisions for TM algorithms, some common TM implementations,
relations of TM algorithms to universal constructions, computability, performance results and tradeoffs in TM Computing.
Christos Kozyrakis
Title: Hardware Support for Transactional Memory: the Debut
Abstract:
The end of single-thread performance scaling made it necessary to investigate technologies
that can reduce the complexity of parallel programming for multi-core chips. Transactional
Memory (TM) quickly emerged as one of the most promising technologies towards this goal. With
TM, programmers simply declare that code blocks operating on shared data should execute as
atomic and isolated transactions with respect to all other code. Concurrency control as
multiple transactions execute in parallel is the responsibility of the system.
This talk will focus on hardware support for transactional execution which is now finding
its way into commercial multi-core chips. Hardware is necessary in order to address the
significant overheads of software TM implementations and provide practical functionality without
surprising results for common coding patterns. We will review the two general approaches for
hardware support for TM, discuss their interface to software, and show that they are practical
within the scope of modern multi-core chips. Moreover, we will show that the hardware
mechanisms for TM can also support useful features for challenges beyond concurrency
control, such as availability, security, and debugging. Finally, we will discuss the tradeoffs
in the commercial implementations of hardware support for transactional execution.
Bio:
Christos Kozyrakis is an Associate Professor of Electrical Engineering & Computer Science at
Stanford University. He works on architectures, runtime environments, and programming models
for parallel computing systems. At Berkeley, he developed the IRAM architecture, a novel
media-processor system that combined vector processing with embedded DRAM technology. At Stanford,
he co-led the Transactional Coherence and Consistency (TCC) project at Stanford that developed
hardware and software mechanisms for programming with transactional memory. He also led the
Raksha project, that developed practical hardware support and security policies to deter high-level
and low-level security attacks against deployed software. Dr. Kozyrakis is currently working on
hardware and software techniques for next-generation data centers. He is also a member of the
Pervasive Parallelism Lab at Stanford, a multi-faculty effort to make parallel computing practical
for the masses.
Christos received a BS degree from the University of Crete (Greece) and a PhD degree from the
University of California at Berkeley (USA), both in Computer Science. He is the Willard R. and Inez
Kerr Bell faculty scholar at Stanford and a senior member of the ACM and the IEEE. Christos has
received the NSF Career Award, an IBM Faculty Award, the Okawa Foundation Research Grant, and a
Noyce Family Faculty Scholarship.
Mark Moir
Title: Transactional memory algorithms, language features, and implementation
Abstract:
I will discuss a variety of ways in which transactional memory can be
used to improve on non-TM-based concurrent algorithms and data
structures in terms of performance, scalability, simplicity, and
usability. I will also discuss proposed transactional language features
for C++, highlight some of the tradeoffs and challenges involved in
specifying and implementing them, and describe some of the alternatives
for implementing these features using hardware and/or software
transactional memory.